1. Field of the Invention
The invention relates to Integrated Circuits, more particularly it relates to a method a device for On-Chip timing characterization of Integrated Circuits (ICs).
2. Description of the Related Art
The setup time of any circuit is the minimum time between one reference signal (clock or gate or any such signal) and other reference signal (data or address) that produces the desired output i.e., there is no functionality failure.
Any chip characterization involves timing measurements. With shrinking technology the timings that are to be measured are also shrinking. Conventionally an external tester at Input/Output (IO) pad level measures the setup timings of ICs. In this case the timings generated by the tester are applied at the IO pads of the embedded macro whose setup timing are to be characterized. Such measurements using separate testing devices are difficult because signal communication from one device to other, itself adds larger noise than the order measurements. Also with this type of testing it is not possible to characterize the setup of a whole data bus accurately as skews can change till reaching the actual block, thus worst-case failure is not checked.
To characterize the timings on the order of picoseconds, the off-chip methods for timing characterization provide ambiguous results, since the delays in the tester are significant to attribute errors in the measurements. Further the methods and devices proposed so far use full custom components or some calibration with respect to the tester. It is important to note that no matter how well the operating and manufacturing conditions are matched, it is impossible to make two identical ICs, hence to calibrate or characterize two different ICs with a custom component on a same scale results in the inaccurate measurements. Therefore it is required to know the delay parameters of individual ICs before they are characterized. Also the temperature and operating voltages affect ICs in different manners, which changes the internal setup time accordingly. Therefore, it is important to account for such conditions while the ICs are being characterized. The present arts do not take this effect into account.
U.S. Pat. No. 5,544,175 provides a method and device in which the delay is provided as a multiple of time increments dT. This incrementing process is Voltage and temperature dependent and also varies chip to chip. Thus for every different condition dT needs to be known. Also, the delay's on-chip value at that particular conditions is also not available. It uses a clock signal as reference to store the status of signals so this results in error of 2*dT when comparing values of 2 signals. The methodology only sees the state of signals and is not able to determine the input constraints of timings of 2 signals or between a signal and bus and uses preprogrammed base delay to calibrate the delay attributable to tester components (column 6). It uses comparators which may be avoided for timing faults measurement.
U.S. Pat. No. 5,787,092 describes a method to measure path delay by changing the clock frequency supplied by a tester which has limitations in terms of accuracy and range. The accuracy in the method is dependent on clock accuracy.
In the U.S. Pat. No. 6,462,998 the delays are made independent of voltage variations by using a regulated voltage supply for voltage and temperature variations. It also uses a voltage controlled delay line that requires careful designing and larger cycle time. This method also uses many full custom components which need to be designed hence requires time and efforts.
In some cases designers have to rely on the value of setup time characterized by Computer Aided Design (CAD) after adding tolerable margins that limit the operating frequency to a value beyond which the circuit can operate successfully, therefore limits the speed of the circuit.
Thus it has been observed that there are needs to develop an on-chip technique that can overcome the above limitations.